Researchers at the University of Illinois at Chicago developed a new thermal control method for gallium nitride (GaN). GaN transistors have higher power densities than conventional silicon transistors and can operate at higher temperatures (below 500 ° C), but as with all semiconductors, GaN transistors also generate excessive heat, which limits their performance. Based on the radiator and fan cooling method to increase the cost and size. Now a research team from the University of Illinois Institute of Micro and Nanotechnology has created a new approach that they claim is simple and low cost. Using computer-aided design, Kan Bailam's team has demonstrated that the thickness of the GaN layer can play a large part in overheating, affecting the thermal and final performance of the device. "The thinner, the colder," says Byram, "traditional GaN transistors are deposited on thick substrates (such as silicon and silicon carbide), but this is not an ideal thermal conductor," says Bayram, whose challenge lies in the traditional Epitaxial mismatch on the substrate leads to tens of micrometer thick devices, and in many cases hundreds of micrometers. "This has a very bad effect on heat dissipation, considering the heat source shrinks at the submicron level as the gate shrinks," says Baram. Using novel semiconductor release methods such as smart dicing and peeling, a GaN transistor that can be released from the rest of the epitaxial and thick substrate can benefit from improved thermal control. "By refining the device layer, the hot spot temperature of high-power GaN transistors can be reduced by 50 ° Celsius," said Baram. Cohen Parker, the research leader, thinks there is a limit to device thickness. "If you cut too much, you get the opposite effect, actually increasing the temperature inside the equipment," Parker said. For typical devices, the best thickness is about a micron. They say this work is important because it provides guidelines for thermal control of GaN-based transistors. The optimum layer size is closely related to the device's thermal interface barrier (TBR), which is a condition of the GaN epitaxial layer and other interfaces. "The best thickness to reduce the hot spot temperature for GaN transistors is determined by the different values ​​of TBR," Parker said. "In addition, the size of the layer depends on how the device will be used. If it is for higher power applications, you'd ideally need more Thin, sub-micron thick layer. " The next step for the Illinois team is to study the electrical properties of GaN layers, such as engineering diamonds and epitaxial graphene, before actually making GaN transistors on the substrate. The Illinois study was funded by the AFOSR Youth Research Grant: FA9550-16-1-0224; the results were published in the Applied Physics Letters B1 layout on October 10, 2016. Friction And Wear Testing Machine
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